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TDA8757
Triple 8-bit ADC 170 Msps
Rev. 07 -- 28 February 2002 Preliminary data
1. General description
The TDA8757 is a triple 8-bit ADC for the digitizing of large bandwidth RGB/YUV signals at a sampling rate up to 170 Msps. The IC supports display resolutions up to 1600 x 1200 (UXGA) at 60 Hz. The IC also includes a PLL that can be locked to the horizontal line frequency and generates the ADC clock. The PLL jitter is minimized for high resolution PC graphics applications. An external clock signal can also be used to clock the ADC. The outputs are available either on one port up to 110 Msps or on two ports up to 170 Msps. The operating mode is selectable with the serial interface to for either I2C-bus or 3-wire serial bus (3W-bus) operation. The clamp level, the gain and the other settings are controllable through the serial interface.
2. Features
s Triple 8-bit ADC s Sampling rate up to 170 Msps s IC controllable by a serial interface which can be I2C-bus or 3W-bus, selected by a TTL input pin s Three clamps for programming a clamping code from -63.5 to +64 in steps of 1 LSB (RGB) and from +120 to +136 in steps of 1 LSB (YUV) 2 2 s Three controllable amplifiers: gain controlled by the serial interface to produce a full-scale resolution of 12 LSB peak-to-peak s Amplifier bandwidth of 250 MHz s Low gain variation with temperature s PLL controllable through the serial interface to generate the ADC clock which can be locked to any line frequency of 15 to 150 kHz s Integrated PLL divider s Programmable phase clock adjustment cells s Internal voltage regulators s TTL compatible digital inputs and outputs s Outputs on one port or demultiplexed on two ports; selectable with the serial interface s Chip enable, high-impedance ADC output s Power-down mode s 1.5 W power dissipation s Sync on green extractor.
Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
3. Applications
s s s s RGB/YUV high-speed digitizing LCD panels drive LCD projection systems VGA to UXGA (1600 x 1200 at 60 Hz) modes.
4. Quick reference data
Table 1: Symbol VCCA VDDD VCCD VCCO VCCA(PLL) VCCO(PLL) ICCA IDDD ICCD ICCO ICCA(PLL) fclk fref(PLL) fPLL INL Quick reference data Parameter analog supply voltage for PLL and the RGB channels logic supply voltage for I2C-bus and 3W-bus digital supply voltage output stages supply voltage for PLL and the RGB channels analog PLL supply voltage output PLL supply voltage analog supply current for the RGB channels logic supply current for I2C-bus and 3W-bus digital supply current output stages supply current analog PLL supply current clock frequency PLL reference clock frequency output clock frequency range DC integral non-linearity from analog input to digital output; full-scale; sinusoidal input; fclk = 170 MHz from analog input to digital output; full-scale; sinusoidal input; fclk = 170 MHz normal (Dmx = 0) de-multiplexed (Dmx = 1) Conditions Min 4.75 4.75 4.75 4.75 4.75 4.75 - - - - - - - 15 10 - Typ 5.0 5.0 5.0 5.0 5.0 5.0 135 1 95 80 34 - - - - 0.5 Max 5.25 5.25 5.25 5.25 5.25 5.25 - - - - - 110 170 150 170 1.5 Unit V V V V V V mA mA mA mA mA MHz MHz kHz MHz LSB
DNL
DC differential non-linearity
-
0.4
1
LSB
Gamp/T B tset(ADC+AGC)
amplifier gain stability variation Vref = 2.5 V with with temperature 100 ppm/C maximum amplifier bandwidth settling time of the block ADC + AGC -3 dB; Tamb = 25 C input signal settling time <1 ns; settling to 1%; fi = 85 MHz
- 250 -
325 - 4
- - -
ppm/C MHz ns
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TDA8757
Triple 8-bit ADC 170 Msps
Table 1: Symbol DRPLL Ptot
Quick reference data...continued Parameter PLL divider ratio total power dissipation maximum PLL phase jitter (peak-to-peak value) fclk = 170 MHz; sinusoidal input fclk = 170 MHz Conditions Min 100 - - Typ - 1.5 360 Max 4095 - - W ps Unit
jPLL(max)(p-p)
5. Ordering information
Table 2: Ordering information Package Name TDA8757HL HLQFP144 Description plastic, heatsink low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm Version SOT612-1 Type number
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TDA8757
Triple 8-bit ADC 170 Msps
6. Block diagram
CLP 7 5 131 8 6
AGCR GAINCR INR DECR
CLPR BOTR
11 9 MUX
CLAMP ADC RED CHANNEL OUTPUT
8 114 to 121 8 100 to 107 113
VREF
3
A0R to A7R B0R to B7R ORR
AGCG GAINCG ING DECG AGCB GAINCB INB DECB
15 17 21 19 GREEN CHANNEL 8 8
129 18 16 92 to 99 79 to 86 91 29 27 8 BLUE CHANNEL 8 71 to 78 58 to 65 70 HSYNCI
OE CLPG BOTG A0G to A7G B0G to B7G ORG CLPB BOTB A0B to A7B B0B to B7B ORB
26 28 32 30
INSOG SOGO A1 A2 SEN SCL SDA DIS I2C/3W
23 24 38 39 43 47 44 42 37 SYNCHRO EXTRACTOR
CKADC 123 124 PLL REGULATOR 134 133 135 136
TDA8757
SERIAL INTERFACE I2C- BUS or 3W-BUS I2C-bus 1-bit (Hlevel)
CKDATA CKREFO CKEXT INV COAST CKREF
132 HSYNC
4
2
130
141 CZ
140
FCE694
DEC1 DEC2 PD
CP
Fig 1. Block diagram.
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TDA8757
Triple 8-bit ADC 170 Msps
CLP
AGC
OE
CKDMX CLP CLAMP CONTROL VP 150 k IN VREF MUX AGC I2C-bus: 8 bits 8 OUTPUTS A (O) & REGISTER OUTPUTS B DAC 8 8 A0 to A7 B0 to B7 OR
CKADC
ADC
DAC D DR R 5 I2C-bus: REGISTER FINE GAIN ADJUST 5 bits (F) 1
8
I2C-bus: 3 bits (Dmx, Odda, Shift, Blk)
8 1 7 I2C-bus: 7 bits (C) SERIAL I2C-BUS
BOT
REGISTER COARSE GAIN ADJUST
FCE695
GAINC HSYNC SDA SCL
Fig 2. Channel diagram (where stands for R, G or B).
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TDA8757
Triple 8-bit ADC 170 Msps
CZ CP COAST CKEXT INV
I2C-bus: 1 bit +/- (Vlevel) CKREF
Z
I2C-bus: 3 bits (Z) I2C-bus: 5 bits (P)
CKADC
MUX
0/180
I2C-bus: 1 bit (Edge)
PHASE FREQUENCY DETECTOR I2C-bus: 5 bits (Ip, Up, Do)
VCO
PHASE I2C-bus: 1 bit (Ckext) CKDMX I2C-bus: 1 bit (Odda) MUX
I2C-bus: 2 bits (Vco)
I2C-bus: 2 bits (Ckdd, Ckdp)
+/-
CKDATA
DIV N (100 to 4095) I2C-bus: 12 bits (Di) MUX SYNCHRO
/2
I2C-bus: 1 bit (Dmx)
+/- I2C-bus: 1 bit (Ckrp)
CKREFO
I2C-bus: 1 bit (Ckrs)
MBL365
OE (1)
(1) Enable of CKDATA and CKREFO by OE. Available in C3 version only.
Fig 3. PLL diagram.
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TDA8757
Triple 8-bit ADC 170 Msps
7. Pinning information
7.1 Pinning
127 n.c. 126 VCCO(PLL) 143 VCCA(PLL) 122 OGNDPLL 142 AGNDPLL 139 AGNDPLL 138 n.c.
112 VCCO(R) 111 OGNDR
110 VCCO(R)
124 CKREFO
123 CKDATA
n.c. DEC2 VREF DEC1 AGCR BOTR GAINCR CLPR DECR VCCA(R) INR n.c. AGNDR n.c. AGCG BOTG GAINCG CLPG DECG VCCA(G) ING AGNDG INSOG SOGO n.c. AGCB BOTB GAINCB CLPB DECB VCCA(B) INB AGNDB n.c. n.c. n.c.
109 OGNDR 108 n.c. 107 B7R 106 B6R 105 B5R 104 B4R 103 B3R 102 B2R 101 B1R 100 B0R 99 A7G 98 A6G 97 A5G 96 A4G 95 A3G 94 A2G 93 A1G 92 A0G 91 ORG 90 VCCO(G) 89 OGNDG 88 VCCO(G) 87 OGNDG 86 B7G 85 B6G 84 B5G 83 B4G 82 B3G 81 B2G 80 B1G 79 B0G 78 A7B 77 A6B 76 A5B 75 A4B 74 A3B 73 A2B
128 DGND1
132 HSYNC
135 COAST
137 VCCD1
136 CKREF
134 CKEXT
125 TESTO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
TDA8757HL
I2C/3W 37
A1 38
A2 39
TCK 40
TDO 41
DIS 42
SEN 43
SDA 44 VDDD 45 VSSD1 46
SCL 47
n.c. 48
n.c. 49
n.c. 50
n.c. 51
VCCD2 52
DGND2 53
n.c. 54
VSSD2 55 VSSD3 56
n.c. 57
B0B 58
B1B 59
B2B 60
B3B 61
B4B 62
B5B 63
B6B 64
B7B 65 OGNDB 66 VCCO(B) 67 OGNDB 68
113 ORR
121 A7R 120 A6R
119 A5R
118 A4R 117 A3R
116 A2R
115 A1R 114 A0R
131 CLP
133 INV
144 n.c.
129 OE
140 CP
130 PD
141 CZ
VCCO(B) 69
ORB 70
A0B 71
A1B 72
GNDDP
FCE697
Fig 4. Pin configuration.
7.2 Pin description
Table 3: Symbol n.c. DEC2 VREF DEC1
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Pin description Pin 1 2 3 4 Description not connected main regulator decoupling input 2 gain stabilizer voltage reference input main regulator decoupling input 1
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TDA8757
Triple 8-bit ADC 170 Msps
Pin description...continued Pin 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Description red channel AGC output red channel ladder decoupling input (BOT) red channel gain capacitor input red channel clamp capacitor input red channel regulator decoupling input red channel analog supply voltage red channel analog input not connected red channel gain analog ground not connected green channel AGC output green channel ladder decoupling input (BOT) green channel gain capacitor input green channel clamp capacitor input green channel regulator decoupling input green channel analog supply voltage green channel analog input green channel gain analog ground sync on green channel input composite sync output not connected blue channel AGC output blue channel ladder decoupling input (BOT) blue channel gain capacitor input blue channel clamp capacitor input blue channel regulator decoupling input blue channel analog supply voltage blue channel analog input blue channel gain analog ground not connected not connected not connected selection input between I2C-bus (active HIGH) and 3W-bus (active LOW) I2C-bus address control input 1 I2C-bus address control input 2 scan test mode input (active HIGH) scan test output I2C-bus and 3W-bus disable control input (disable at HIGH level) select enable input for 3W-bus
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Table 3: Symbol AGCR BOTR GAINCR CLPR DECR VCCA(R) INR n.c. AGNDR n.c. AGCG BOTG GAINCG CLPG DECG VCCA(G) ING AGNDG INSOG SOGO n.c. AGCB BOTB GAINCB CLPB DECB VCCA(B) INB AGNDB n.c. n.c. n.c. I2C/3W A1 A2 TCK TDO DIS SEN
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TDA8757
Triple 8-bit ADC 170 Msps
Pin description...continued Pin 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Description I2C-bus/3W-bus serial data input logic I2C-bus/3W-bus digital supply voltage logic I2C-bus/3W-bus digital ground 1 I2C-bus/3W-bus serial clock input not connected not connected not connected not connected digital supply voltage 2 digital ground 2 not connected logic I2C-bus/3W-bus digital ground 2 logic I2C-bus/3W-bus digital ground 3 not connected blue channel ADC output B bit 0 (LSB) blue channel ADC output B bit 1 blue channel ADC output B bit 2 blue channel ADC output B bit 3 blue channel ADC output B bit 4 blue channel ADC output B bit 5 blue channel ADC output B bit 6 blue channel ADC output B bit 7 (MSB) blue channel ADC output B ground blue channel ADC output B supply voltage blue channel ADC output A ground blue channel ADC output A supply voltage blue channel ADC output bit out of range blue channel ADC output A bit 0 (LSB) blue channel ADC output A bit 1 blue channel ADC output A bit 2 blue channel ADC output A bit 3 blue channel ADC output A bit 4 blue channel ADC output A bit 5 blue channel ADC output A bit 6 blue channel ADC output A bit 7 (MSB) green channel ADC output B bit 0 (LSB) green channel ADC output B bit 1 green channel ADC output B bit 2 green channel ADC output B bit 3 green channel ADC output B bit 4 green channel ADC output B bit 5
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Table 3: Symbol SDA VDDD VSSD1 SCL n.c. n.c. n.c. n.c. VCCD2 DGND2 n.c. VSSD2 VSSD3 n.c. B0B B1B B2B B3B B4B B5B B6B B7B OGNDB VCCO(B) OGNDB VCCO(B) ORB A0B A1B A2B A3B A4B A5B A6B A7B B0G B1G B2G B3G B4G B5G
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TDA8757
Triple 8-bit ADC 170 Msps
Pin description...continued Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 Description green channel ADC output B bit 6 green channel ADC output B bit 7 (MSB) green channel ADC output B ground green channel ADC output B supply voltage green channel ADC output A ground green channel ADC output A supply voltage green channel ADC output bit out of range green channel ADC output A bit 0 (LSB) green channel ADC output A bit 1 green channel ADC output A bit 2 green channel ADC output A bit 3 green channel ADC output A bit 4 green channel ADC output A bit 5 green channel ADC output A bit 6 green channel ADC output A bit 7 (MSB) red channel ADC output B bit 0 (LSB) red channel ADC output B bit 1 red channel ADC output B bit 2 red channel ADC output B bit 3 red channel ADC output B bit 4 red channel ADC output B bit 5 red channel ADC output B bit 6 red channel ADC output B bit 7 (MSB) not connected red channel ADC output B ground red channel ADC output B supply voltage red channel ADC output A ground red channel ADC output A supply voltage red channel ADC output A bit out of range red channel ADC output A bit 0 (LSB) red channel ADC output A bit 1 red channel ADC output A bit 2 red channel ADC output A bit 3 red channel ADC output A bit 4 red channel ADC output A bit 5 red channel ADC output A bit 6 red channel ADC output A bit 7 (MSB) PLL digital ground output data clock output horizontal pulse synchronized to pixel clock output reserved for test
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Table 3: Symbol B6G B7G OGNDG VCCO(G) OGNDG VCCO(G) ORG A0G A1G A2G A3G A4G A5G A6G A7G B0R B1R B2R B3R B4R B5R B6R B7R n.c. OGNDR VCCO(R) OGNDR VCCO(R) ORR A0R A1R A2R A3R A4R A5R A6R A7R OGNDPLL CKDATA CKREFO TESTO
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Triple 8-bit ADC 170 Msps
Pin description...continued Pin 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Description PLL output supply voltage not connected digital ground 1 output enable; active LOW (when OE is HIGH, the outputs are high-impedance) power-down control input (IC is in Power-down mode when this pin is HIGH) clamp pulse input (clamp active HIGH) horizontal synchronization pulse input PLL clock output inverter control input (invert when HIGH) external clock input PLL coast control input PLL reference clock input digital supply voltage 1 not connected PLL analog ground PLL filter input PLL filter input PLL analog ground PLL analog supply voltage not connected
Table 3: Symbol VCCO(PLL) n.c. DGND1 OE PD CLP HSYNC INV CKEXT COAST CKREF VCCD1 n.c. AGNDPLL CP CZ AGNDPLL VCCA(PLL) n.c. GNDDP
exposed die pad connection
8. Functional description
This triple high-speed 8-bit ADC is designed to convert RGB/YUV signals, coming from an analog source, into digital data used by a LCD driver (pixel clock up to 170 MHz).
8.1 Analog video inputs
The RGB/YUV video inputs are externally AC coupled and are internally DC polarized. The synchronization signals are also used for the internal PLL and the gain calibration. If the green video signal has composite sync (sync on green), it is possible to extract this composite sync by connecting the green signal to pin INSOG (AC coupled). When the sync pulse amplitude is below 300 mV, the I2C-bus bit `Slevel' has to be set to logic 1 (see Figure 5). The maximum amplitude for the sync pulse is 600 mV. The composite sync is available at pin SOGO (TTL level compatible signal).
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TDA8757
Triple 8-bit ADC 170 Msps
blank level 300 mV to 600 mV 150 mV comparison level set by I2C-bus bit Slevel = 0
blank level 150 mV to 300 mV 80 mV comparison level set by I2C-bus bit Slevel = 1
005aaa009
Fig 5. Sync level diagram.
If this function is not used, pin INSOG should be connected to the analog power supply. In this event, pin SOGO is at LOW-level TTL.
8.2 Clamps
Three independent parallel clamping circuits are used to clamp the video input signals on several black levels. The clamping levels may be set from -63.5 to +64 LSBs (RGB) and from +120 to +136 LSBs in steps of 12 LSB (YUV). They are controlled by changing the values in three 8-bit registers: OFFSETR, OFFSETG and OFFSETB (see Table 5). Each clamp must be able to correct an offset from 100 mV to 10 mV within 300 ns, and correct the total offset in 10 lines. The clamping is done using the following principle: On the incoming of a TTL positive going pulse supplied on pin CLP, three external capacitors are loaded independently by the device in order to change the voltage level of each analog RGB input. The capacitors are connected to pins CLPR, CLPG and CLPB.
video signal
255 constant level
Clamp = +128 Clamp = +64 Clamp =0 Clamp = -63.5
ADC
clamp programming
0 constant level
CLP
FCE698
Fig 6. Clamp definition.
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TDA8757
Triple 8-bit ADC 170 Msps
8.2.1
Variable gain amplifiers Three independent variable gain amplifiers are used to provide a full-scale input signal to the 8-bit ADC for each channel. The gain adjustment range is designed so that for an input range varying from 0.4 to 1.2 V (p-p), the output signal corresponds to the ADC full-scale input of 1 V (p-p). To ensure that the gain does not vary over the whole operating temperature range, a reference voltage Vref = 2.5 V (DC) with a maximum variation of 100 ppm/C, is supplied externally on pin VREF. The calibration of the gains is done using the following principle: On the incoming of a pulse supplied to pin HSYNC, an internal multiplexer switches from the RGB video signals to a reference voltage (116Vref). The ADCs inputs become this reference signal and the three corresponding outputs are compared to pre-set values loaded in three 7-bit registers: COARSER, COARSEG and COARSEB. Depending on the result of the comparisons, the three gains are adjusted such that the ADC outputs become equal to the pre-set values in the registers. The three gains are simply controlled by changing the values in the COARSE registers. The signal supplied on pin HSYNC, may be selected active HIGH or active LOW. The choice is done through the serial interface by setting bit `Hlevel' in the control register (active HIGH when bit Hlevel = 0). This active part of the signal has to occur during the blanking period of the signal in order not to interrupt the active video. Normally the horizontal synchronization signal, provided by the video source, is connected to pin HSYNC. The values loaded in the gain registers (COARSER, COARSEG, COARSEB) are chosen among 68 values (see Table 6). A fine correction is also used to finely tune the gain on the three channels and to compensate the channel-to-channel gain mismatch. The fine correction is done using the following principle: the three binary codes, stored in the three 5-bit registers (FINER, FINEG and FINEB) are converted into three analog voltages (with three DACs) and are independently added to the reference voltage (116Vref). Thus, three different reference voltages are used for the gain calibration of the three channels. When the COARSE registers are set at full-scale, the resolution of the fine registers corresponds to 12 LSB peak-to-peak (see Equation 3).
8.2.2
Important recommendations The clamping and the gain calibration requires two external signals (pulses). One signal is connected to pin CLP and the other is connected to pin HSYNC. It is very important that:
* The active part of these two signals occur during the blanking of the video signal,
in order not to interrupt or disturb the active video.
* The active part of these two signals does not overlap on each other, in order to
perform correctly the gain calibration and the clamping. Normally the clamp pulse is sent after the end of the horizontal synchronization pulse.
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TDA8757
Triple 8-bit ADC 170 Msps
8.2.3
ADCs Three ADCs convert analog signals into three series of 8-bit codes, with a maximum clock frequency of 170 Msps. The ADCs input range is 1 V (p-p) full-scale and the pipeline delay is 1 clock cycle from the sampling to the data output. The reference ladder regulators are integrated.
8.2.4
Data outputs ADC outputs are straight binary. Pin OE switches the output status between active and high-impedance (OE = HIGH). It is possible to force the outputs with a maximum 10 pF capacitive load. The timing must be checked very carefully if the capacitive loads are more than 10 pF. It is possible to force the outputs to logic 0 during the gain calibration (during HSYNC pulse) and during the clamping (CLP pulse). This mode is activated through the serial interface by setting bit `Blk' to logic 1 in register DEMUX. The TDA8757 provides outputs either on one port (port A) or on two ports (ports A and B). The selection is made with the serial interface by setting bit `Dmx' to logic 0 or logic 1 in register DEMUX. When just one port is used (Dmx = 0), the unused ports are forced to LOW level. When two ports are used (Dmx = 1), it is possible to select the port that would provide the odd pixel by setting bit `Odda' to logic 1 or logic 0 in register DEMUX; when this bit is logic 1, the odd pixel is output on port A. One out-of-range bit exists per channel (ORR, ORG and ORB). It will be at logic 1 when the signal is out-of-range of the ADC voltage ladder. Finally, two configurations are possible: either the port A outputs and the port B outputs are both synchronous or they are interleaved. The selection is done by setting bit `Shift' to logic 0 or logic 1 in register DEMUX.
CKREF
CKADC
CKREFO
OUT A
XXX
XXX
ODD
EVEN
FCE708
Fig 7. Definition of odd and even pixels; Edge = 0, Dmx = 0 and Ckrp = 1.
8.2.5
PLL The ADCs are clocked by either the internal PLL locked to the reference clock CKREF or an external clock connected to pin CKEXT. All parts of the PLL are on-chip except the loop filter capacitance. The selection is performed via the serial interface by setting bit `Ckext' in register PHASE (Ckext = 1 when the external clock is used).
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TDA8757
Triple 8-bit ADC 170 Msps
The reference clock (CKREF) range is between 15 and 150 kHz. Consequently, the VCO minimum frequency is 12 MHz and the maximum frequency is 170 MHz. The gain of the VCO part can be controlled through the serial interface, depending on the frequency range to which the PLL is locked. Moreover, the PLL may be locked either on the rising or on the falling edge of the CKREF signal pulses. This choice is made through the serial interface by setting bit `Edge' in register CONTROL (rising edge when bit `Edge' = 0). The charge pump current (Icp) enables an increase of PLL bandwidth. It is programmable through the serial interface by setting bits `Ip2', `Ip1' and `Ip0' in the control register (see Table 8). Different resistance values (R) for the filter can also be programmed through the serial interface by setting the bits `Z2', `Z1' and `Z0' in register VCO (see Table 9). To have optimal PLL performance, R and Icp must be chosen so that:
* The result of the product `R x Icp' is smaller than a determined limit (Lim) * The result of the product `R x Icp' is as close as possible to this limit (Lim).
0.3 x DR PLL x f ref Lim = -------------------------------------------------K0 where: (1)
* DRPLL = the divider ratio, which is the ratio between the pixel frequency and the
horizontal line frequency of the incoming signal. The setting of this parameter is performed through the serial interface with bits Di0 to Di11. These bits are present in the VCO-, divider- and phase registers.
* fref = the frequency of the signal. * K0 = the VCO gain, which depends on the pixel frequency ranges given in
Table 10. In the event that several combinations of R and Icp give the same result, a calculation of the damping factor () for each combination becomes necessary. The combination of R and Icp whose damping factor is the closest to 1.5, generates the optimal PLL performance. K 0 I cp R CZ = -------------- ---------------------------------------------DR PLL ( C Z + C P ) 2 (2)
where CZ and CP are the external capacitors of the PLL loop filter. The recommended values are: CZ = 68 nF and CP = 150 pF. The COAST signal is used to disconnect the PLL phase frequency detector during the frame flyback (vertical blanking) or during the unavailability of the CKREF signal. This signal can normally be derived from the VSYNC signal. COAST may be set either active HIGH or active LOW by setting bit `Vlevel' in the control register through the serial interface (Vlevel = 0 when HIGH).
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TDA8757
Triple 8-bit ADC 170 Msps
It is possible to control the phase of the ADC clock (CKADC) through the serial interface with the included digital phase-shift controller. The phase register (5 bits) enables the phase to shift by steps of 11.25 . The CKREF signal is re-synchronized by the synchro-block on the CKADC clock. The new reference is available on pin CKREFO. This synchronization may be done with the CKREF signal directly, or with the output of the divider in the PLL (see Figure 3). The selection is done via the serial interface by setting bit `Ckrs' in the phase register (Ckrs = 1 when the CKREF signal is used). The polarity of the signal on pin CKREFO is controlled through the serial interface by setting bit `Ckrp' in register DEMUX (positive polarity if Ckrp = 0). The width of this signal is fixed to 8 clock cycles. The PLL also provides a CKDATA clock. This clock is synchronized on the data outputs whatever the output mode. It is possible to delay the CKDATA clock with a constant time ( = 3 ns, compared to the outputs) by setting bit `Ckdd' to logic 1 in register DEMUX. It is also possible to reverse the CKDATA clock, referenced to the outputs, by setting bit `Ckdp' in register DEMUX. The maximum capacitive load for each clock output is 10 pF, and pin OE switches the output status between active and high impedance (OE = HIGH). If an external clock is used, it has to be connected to pin CKEXT. Bit `Ckext' and bit `Ckrs' in the phase register have to be set at logic 1, and it is also important to disconnect the internal PLL by using the following settings:
* Set bit `Do' in the control register to logic 1. * Set bits `Vco1' and `Vco0' in register VCO to logic 0.
CKREF tCKAO CKADC tCKREFO CKREFO Ckrp = 0 8 clock periods CKREFO Ckrp = 1
FCE699
Fig 8. Timing diagram; CKREFO; Dmx = 0.
There is a delay between the input signal on pin CKREF and the corresponding output on pin CKREFO; see Figure 8. This delay is tCKREFO: tCKREFO = either tCKAO (if clock phase >01000) or tCKAO + TCLK(pixel) (if phase <01000) tCKAO = tCLK(buffer) + tphase selector phase tCLK(buffer) = tbf and tphase selector = --------------- T CLK ( pixel ) 2
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Triple 8-bit ADC 170 Msps
9. I2C-bus and 3W-bus interfaces
9.1 Register definitions
The configuration of the registers is given in Table 4.
Table 4: Function name SUBADDR OFFSETR X COARSER X FINER X OFFSETG X COARSEG X FINEG OFFSETB FINEB VCO DIVIDER (LSB) PHASE DEMUX X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 I2C-bus and 3W-bus registers Subaddress Bit definition LSB X Or6 Cr6 X Og6 Cg6 X Ob6 Cb6 X Z1 Di7 Ckrs Cken X Or5 Cr5 X Og5 Cg5 Ob5 Cb5 X Z0 Di6 Ckext Ckrp Mode Sa3 Or4 Cr4 Fr4 Og4 Cg4 Ob4 Cb4 Fb4 Up Vco1 Di5 P4 Ckdp Or3 Cr3 Fr3 Og3 Cg3 Fg3 Ob3 Cb3 Fb3 Do Vco0 Di4 P3 Ckdd Sa2 Or2 Cr2 Fr2 Og2 Cg2 Fg2 Ob2 Cb2 Fb2 Ip2 Di11 Di3 P2 Shift Sa1 Or1 Cr1 Fr1 Og1 Cg1 Fg1 Ob1 Cb1 Fb1 Ip1 Di10 Di2 P1 Sa0 Or0 Cr0 Fr0 Og0 Cg0 Fg0 Ob0 Cb0 Fb0 Ip0 Di9 Di1 P0 X Or7 Or8 X Og7 Og8 X Ob7 Ob8 X Z2 Di8 Di0 Blk A7 A6 A5 A4 A3 A2 A1 A0 MSB Default value XXX1 0000 0111 1111 0010 0000 XXX0 0000 0111 1111 0010 0000 XXX0 0000 0111 1111 0010 0000 XXX0 0000 0000 0111 1011 1011 0100 1100 0000 0000 1000 0111
Slevel Fg4
COARSEB X CONTROL X
Vlevel Hlevel Edge
Odda Dmx
9.1.1
Subaddress All the registers are defined by a subaddress of 7 bits: bit Mode refers to the mode which is used with the I2C-bus interface, bits `Sa3' to `Sa0' give the subaddress of each register. Bit Mode, used only with the I2C-bus, allows two modes for the programming: Mode 0 Mode 1 Each register is programmed independently, by giving its subaddress and its content. All the registers are programmed one after the other, by giving this initial condition (XXX1 1111) as the subaddress state; thus, the registers are changed following the predefined sequence of 16 bytes (from subaddress 0000 to 1101).
The default values correspond to a VESA 1280 x 1024 at 75 Hz graphic mode. 9.1.2 Offset register This register controls the clamp level for the RGB channels. The relationship between the programming code and the level of the clamp code is given in Table 5.
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TDA8757
Triple 8-bit ADC 170 Msps
Coding Clamp code -63.5 -63 -62.5 ... 0 ... 63.5 64 120 ... 136 0 ... 63 or 64 64 120 ... 136 underflow ADC output
Table 5: 0 1 2 ... 127 ... 254 255 256 ... 287
Programmed code
The default programmed value is:
* Programmed code = 127 * Clamp code = 0 * ADC output = 0.
9.1.3 Coarse and Fine registers These two registers enable the gain control: the AGC gain with the coarse register, and the reference voltage with the fine register. The coarse register programming equation is as follows: N COARSE + 1 N COARSE + 1 1 GAIN = ----------------------------------------------- x ----- = ----------------------------------------------- x 32 V ref . ( 512 - N FINE - 16 ) N FINE V ref 1 - ----------------- 32 x 16 Where: Vref = 2.5 V. The gain correspondence is given in Table 6. The gain is linear with reference to the programming code (NFINE = 0).
Table 6: NCOARSE 32 99 Typical gain correspondence (COARSE) Gain 0.825 2.5 Vi to be full-scale (V) 1.212 0.4
(3)
The default programmed value is as follows:
* NCOARSE = 32 * Gain = 0.825 * Vi to be full-scale = 1.212.
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Triple 8-bit ADC 170 Msps
To modulate this gain, the fine register is programmed using the above equation. With a full-scale ADC input, the fine register resolution is a 12 LSB peak-to-peak (see Table 7 for NCOARSE = 32).
Table 7: NFINE 0 31 Typical gain correspondence (FINE) Gain 0.825 0.878 Vi to be full-scale (V) 1.212 1.139
The default programmed value is: NFINE = 0. 9.1.4 Control register COAST and HSYNC signals can be derived by setting the I2C-bus control bits `Vlevel' and `Hlevel' respectively. When bits `Vlevel' and `Hlevel' are set to zero, COAST and HSYNC are active HIGH. Bit `Edge' defines the rising or falling edge of CKREF to synchronize the PLL. It will be on the rising edge if the bit is a logic 0 and on the falling edge if the bit is at logic 1. Bits `Up' and `Do' are used for the test, to force the charge pump current. These bits have to be logic 0 during normal use. Bit `Cken' is used for the test to check the CKADC internal signal. This bit has to be logic 0 during normal use. Bits `Ip0', `Ip1' and `Ip2' control the charge pump current, to increase the bandwidth of the PLL, as shown in Table 8.
Table 8: Ip2 0 0 0 0 1 1 1 1 Charge pump current control Ip1 0 0 1 1 0 0 1 1 Ip0 0 1 0 1 0 1 0 1 Current (A) 6.25 12.5 25 50 100 200 400 700
The default programmed value is as follows:
* * * *
9.1.5
Charge pump current = 700 A Bits `Up' and `Do' are used for testing, normally they are set to logic 0 Rising edge of CKREF: bit `Edge' at logic 0 COAST and HSYNC inputs are active HIGH: bits `Vlevel' and `Hlevel' at logic 0.
VCO register Bits `Z2', `Z1' and `Z0' enable the internal resistance for the VCO filter to be selected.
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Triple 8-bit ADC 170 Msps
VCO register bits Z1 0 0 1 1 0 0 1 1 Z0 0 1 0 1 0 1 0 1 Resistance (k) high-impedance 9 6.4 4.5 3.2 2.25 1.6 1.1
Table 9: Z2 0 0 0 0 1 1 1 1
Bits `Vco1' and `Vco0' control the VCO gain.
Table 10: VCO gain control Vco1 Vco0 VCO gain (MHz/V) Pixel clock frequency range (MHz) 10 to 20 20 to 40 40 to 85 85 to 170
0 0 1 1
0 1 0 1
12 20 40 70
The default programmed value is as follows:
* Internal resistance = 2.25 k * VCO gain = 70 MHz/V.
9.1.6 Divider register This register controls the PLL frequency. Bits `Di8' to `Di0' are the LSB bits. The default programmed value is 0110 1001 1000 = 1688. The MSB bits (`Di11', `Di10' and `Di9') and the LSB bit `Di0' have to be programmed before bits `Di8' to `Di1' in order to have the required divider ratio. Bit `Di0' is used for the parity divider number (Di0 = 0: even number; Di0 = 1: odd number). It should be noted that if the I2C-bus programming is done in mode 1 and the bit `Di0' has to be toggled, then the registers have to be loaded twice to update the divider ratio. 9.1.7 Phase register Bit `Ckext' is logic 0 when the PLL clock is used, and logic 1 when the external clock is used. Bit `Ckrs' is logic 1 when the synchronization is done with CKREF (see Figure 3). Bits `P4' to `P0' are used to program the phase shift for the clock pixel.
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Triple 8-bit ADC 170 Msps
Table 11: Phase registers bits P4 0 0 ... 1 1 P3 0 0 ... 1 1 P2 0 0 ... 1 1 P1 0 0 ... 1 1 P0 0 1 ... 0 1 Phase shift (deg) 0 11.25 ... 337.5 348.75
The default programmed value is as follows:
* No external clock: bit `Ckext' is logic 0 * Phase shift for CKDATA is 0 degrees.
9.1.8 DEMUX register The default programming is:
* * * * * * *
9.1.9
Outputs forced to logic 0 during CLP and HSYNC pulses: bit `Blk' = 1 CKREFO with positive polarity: bit `Ckrp' = 0 CKDATA not reversed: bit `Ckdp' = 0 CKDATA not delayed: bit `Ckdd' = 0 De-multiplexed outputs: bit `Dmx' = 1 Interleaved outputs: bit `Shift' = 1 Odd pixels on port A: bit `Odda' = 1.
Power-down mode
* When the supply is completely switched off, the registers are set to their default
values; in that event they have to be reprogrammed if the required settings are different (e.g. through an EEPROM)
* When the device is in Power-down mode (pin PD = HIGH), the previously
programmed register values remain unaffected.
9.2 I2C-bus protocol
Table 12: Register format A6 1 A5 0 A4 0 A3 1 A2 1 A1 A2 A0 A1 RW 0
The address of the circuit for the I2C-bus is 1001 1XX0. Bits `A1' and `A0' are fixed by the potential on pins A2 and A1. Bit `RW' must always be equal to logic 0 because it is not possible to read the data in the register. The timing and protocol for the I2C-bus are standard. Two sequences are available; see Table 13 and 14.
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Triple 8-bit ADC 170 Msps
Table 13: Address sequence for mode 0 S = START condition, A = acknowledge bit (generated by the device) and P = STOP condition. S IC ADDRESS A SUBADDRESS A REGISTER1 DATA REGISTER1 (see Table 4) A SUBADDRESS A REGISTER2 ... P
Table 14: Address sequence for mode 1 S = START condition, A = acknowledge bit (generated by the device) and P = STOP condition. S IC ADDRESS A SUBADDRESS A XX11 1111 DATA REGISTER1 (see Table 4) A DATA REGISTER2 A ... P
9.3 3W-bus protocol
For the 3W-bus, the first byte refers to the register address which is programmed. The second byte refers to the data to be sent to the chosen register (see Table 4). Using a 3W-bus interface, an indefinite number of ICs can operate on the same system. Pin SEN is used to validate the circuits.
t r3W = 600 ns
100 ns
SEN
1 SCL
9
1
9
SDA
x
x
x
x
A3 A2 A1 A0
x
D7 D6 D5 D4 D3 D2 D1 D0
x
FCE707
t s3W = 100 ns
t h3W = 100 ns
Fig 9. 3W-bus protocol.
10. Limiting values
Table 15: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCCA VDDD VCCD VCCO Parameter analog supply voltage logic supply voltage digital supply voltage output stages supply voltage Conditions Min -0.3 -0.3 -0.3 -0.3 Max +7.0 +7.0 +7.0 +7.0 Unit V V V V
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Triple 8-bit ADC 170 Msps
Table 15: Limiting values...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC Parameter supply voltage differences VCCA - VCCD VCCO - VCCD VCCO - VDDD VCCA - VDDD VCCD - VDDD VCCA - VCCO Vi(RGB) Io Tstg Tamb Tj RGB input voltage range output current storage temperature ambient temperature junction temperature referenced to AGND -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -0.3 - -55 0 - +1.0 +1.0 +1.0 +1.0 +1.0 +1.0 +7.0 10 +150 70 150 V V V V V V V mA C C C Conditions Min Max Unit
11. Thermal characteristics
Table 16: Typical thermal characteristics Symbol Rth(j-a) Parameter thermal resistance from junction to ambient Conditions in free air Value 30 Unit K/W
12. Characteristics
Table 17: Characteristics VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V (referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together; Tamb = 0 to 70 C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 C; unless otherwise specified. Symbol Supplies VCCA(PLL), VCCA(R), VCCA(G), VCCA(B) VDDD VCCD VCCO(PLL), VCCO(R), VCCO(G), VCCO(B) ICCA(PLL) analog supply voltage for PLL and the RGB channels 4.75 5.0 5.25 V Parameter Conditions Min Typ Max Unit
logic supply voltage for I2C-bus and 3W-bus digital supply voltage output stages supply voltage for PLL and the RGB channels
4.75 4.75 4.75
5.0 5.0 5.0
5.25 5.25 5.25
V V V
analog PLL supply current
-
34
-
mA
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Triple 8-bit ADC 170 Msps
Table 17: Characteristics...continued VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V (referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together; Tamb = 0 to 70 C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 C; unless otherwise specified. Symbol ICCA(R), ICCA(G), ICCA(B) IDDD ICCD ICCO(R), ICCO(G), ICCO(B), ICCO(PLL) VCC Parameter analog supply current for the RGB channels logic supply current for I2C-bus and 3W-bus digital supply current output stages supply current for the RGB channels and PLL sinusoidal input Conditions Min - Typ 135 Max - Unit mA
- - -
1 95 80
- - -
mA mA mA
supply voltage difference VCCA - VCCD VCCO - VCCD VCCO - VDDD VCCA - VDDD VCCD - VDDD VCCA - VCCO -0.25 -0.25 -0.25 -0.25 -0.25 -0.25 sinusoidal input - - - - - - - - 1.5 55 +0.25 +0.25 +0.25 +0.25 +0.25 +0.25 - - V V V V V V W mW
Ptot Ppd
total power dissipation power dissipation in Power-down mode bandwidth settling time of the block ADC + AGC
R, G and B amplifiers B tset(ADC+AGC) -3 dB; Tamb = 25 C full-scale (black to white) transition; input signal settling time <1 ns; settling to within 2 LSB minimum coarse gain; code = 32 maximum coarse gain; code = 99 GFINE fine gain correction range minimum fine input code = 0 maximum fine input code = 31 Gamp/T IGC tstab amplifier gain stability variation with temperature gain current amplifier gain adjustment speed from minimum to maximum gain amplifier reference voltage HSYNC active; capacitors on pins 8, 16 and 24 are 22 nF Vref with 100 ppm/C maximum variation 250 - - 4 - - MHz ns
GCOARSE
coarse gain range
- - - - - - -
-1.67 8 0 -0.5 325 20 25
- - - - - - -
dB dB dB dB ppm/C A mdB/s
Vref
-
2.5
-
V
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TDA8757
Triple 8-bit ADC 170 Msps
Table 17: Characteristics...continued VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V (referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together; Tamb = 0 to 70 C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 C; unless otherwise specified. Symbol Iref Vi(p-p) Parameter amplifier reference voltage current input voltage (peak-to-peak value) corresponding to full-scale input at high gain corresponding to full-scale output at low gain Ci GE(rms) input capacitance channel-to-channel gain matching (RMS value) maximum coarse gain; Tamb = 25 C minimum coarse gain; Tamb = 25 C Clamps PCLP precision maximum black level noise on RGB channels = 10 mV; Tamb = 25 C - 0.5 - LSB Conditions Min - - - - - - Typ 50 0.4 - 10 1 5 Max - - 1.212 - - - Unit A V V pF % %
tW(CLP) CLPE Aoff
clamp pulse width channel-to-channel clamp matching code clamp reference clamp register input code = 0 clamp register input code = 255 clamp register input code = 256 clamp register input code = 287
500 - - - - -
- 0.5 -63.5 +64 +120 +135.5
2000 - - - - -
ns LSB LSB LSB LSB LSB
Phase-locked loop (PLL) jPLL(max)(p-p) DR fref fPLL step step ADCs fs INL maximum sampling frequency DC integral non-linearity from IC analog input to digital output; sinusoidal input; fclk = 170 MHz from IC analog input to digital output; sinusoidal input; fclk = 170 MHz
Rev. 07 -- 28 February 2002
long term PLL phase jitter (peak-to-peak value) divider ratio reference clock frequency output clock frequency phase drift [1]
fclk = 170 MHz
- 100 15 10
360 - - - - 11.25 - 0.5
- 4095 150 170 2 - - 1.5
ps - kHz MHz step deg MHz LSB
standard at 160 Msps Tamb = 25 C
- - 170 -
phase shift step
DNL
DC differential non-linearity
-
0.4
1
LSB
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Triple 8-bit ADC 170 Msps
Table 17: Characteristics...continued VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V (referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together; Tamb = 0 to 70 C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 C; unless otherwise specified. Symbol ENOB [2] S/N SFDR ext fclk(max) fclk(max) tCPH tCPL Data td(s) tsu(d)(o) th(o) tdZH tdZL tdHZ tdLZ VOL VOH IOL IOH CL VIL VIH IIL IIH Zi Ci Vsync(G) timing [3] sampling delay time output data set-up time output hold time output enable HIGH output enable LOW output disable HIGH output disable LOW LOW-level output voltage HIGH-level output voltage LOW-level output current HIGH-level output current load capacitance I2C/3W, LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input impedance input capacitance sync on green pulse amplitude [4] Slevel = 0; see Figure 5 Slevel = 1; see Figure 5 Io = 1 mA Io = 1 mA VOL = 0.2 V VOH = 3.4 V all times referenced to 50% of the rising edge of CKDATA; see Figure 10 - - - - - - - - 2.4 - - - OE, CKEXT) - 2.0 - - - - 300 150 - - 400 35 tbf tbf - - 0.8 - - - - - 600 300 V V A A k pF mV mV -7.5 -7 1 15 18 13 10 - - 0.2 0.3 10 - - - - - - - 0.4 - - - - ns ns ns ns ns ns ns V V mA mA pF Parameter effective number of bits signal-to-noise ratio spurious free dynamic range ADC clock duty factor maximum clock frequency maximum clock frequency clock pulse width HIGH clock pulse width LOW fclk = 170 MHz fclk = 170 MHz Conditions Min - - - 45 - - 2.5 2.5 Typ 7.4 46 57 50 - - - - Max - - - 55 170 170 - - Unit bits dB dB % MHz MHz ns ns
Signal-to-noise ratio Spurious free dynamic range Clock timing output (CKDATA)
Clock timing input (CKEXT)
3-state output delay time
Data and sync outputs
TTL digital inputs (CKREF, COAST, INV, HSYNC, CLP, PD, DIS,
Sync on green input
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TDA8757
Triple 8-bit ADC 170 Msps
Table 17: Characteristics...continued VCCA = 4.75 V to 5.25 V (referenced to AGND); VCCD = 4.75 V to 5.25 V (referenced to DGND); VDDD = 4.75 V to 5.25 V (referenced to VSSD); VCCO = 4.75 V to 5.25 V (referenced to OGND); AGND, DGND, OGND and VSS connected together; Tamb = 0 to 70 C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 C; unless otherwise specified. Symbol 3W-bus trst tsu th I2C-bus [5] VIL VIH LOW-level input voltage HIGH-level input voltage for SCL and SDA for SCL and SDA; VPU = 5 V for SCL and SDA; VPU = 3 V fSCL tBUF tHD;STA tSU;STA tLOW tHIGH tSU;DAT tHD;DAT tr tf tSU;STO Cb
[1] [2]
Parameter reset time of the chip before 3-wire communication data set-up time for 3-wire communication data hold time for 3-wire communication
Conditions
Min - - -
Typ 600 100 100
Max - - -
Unit ns ns ns
- 3 0.7VDD 0 4.7 4.0
- - - - - - - - - - - - - - -
0.3VDD - - 100 - - - - - - - 1.0 300 - 400
V V
clock frequency time the bus must be free before new transmission can start start condition hold time start condition set-up time LOW-level clock period HIGH-level clock period data set-up time data hold time SDA and SCL rise time SDA and SCL fall time stop condition set-up time bus line capacitive loading fSCL = 100 kHz fSCL = 100 kHz repeated start
kHz s s s s s ns ns s ns s pF
4.7 4.7 4.0 250 0 - - 4.0 -
[3] [4] [5]
From 25 to 70 C, the edge of the clock CKDATA has a shift of 1 phase compared to CKREF. Effective bits are obtained from a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST frequency). Conversion-to-noise ratio: S/N = EB x 6.02 + 1.76 dB. Output data acquisition: the output data is available after the maximum sampling delay time td(s). All the timings are given for a 10 pF capacitive load. Pulse relative to the blank level. The I2C-bus timings are given for use of the bus at a frequency of 100 kbit/s (100 kHz). This bus could be used at a frequency of 400 kbit/s (400 kHz).
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Triple 8-bit ADC 170 Msps
Table 18: Examples of PLL settings and performance VCCA = VDDD = VCCD = VCCO = 5 V; Tamb = 25 C. Video standards fref (kHz) fclk (MHz) N KO CZ CP (MHz/V) (nF) (nF) 20 40 40 70 70 70 68 68 68 68 68 68 0.15 0.15 0.15 0.15 0.15 0.15 IP Z Long-term time jitter [1] (A) (k) RMS-value peak-to-peak (ps) value (ps) 200 700 400 400 400 400 4.5 1.6 4.5 3.2 4.5 4.5 242 225 120 98 70 65 1452 1350 720 588 420 390
VGA: 640 x 480 VESA: 800 x 600 (SVGA 72 Hz) VESA: 1024 x 768 (XGA 75 Hz) VESA: 1280 x 1024 (SXGA 60 Hz) VESA: 1280 x 1024 (SXGA 75 Hz) VESA: 1600 x 1200 (UXGA 60 Hz)
[1]
31.469 25.175 800 48.08 60.02 63.98 80.00 75.00 50 78.75 108 135 162 1040 1312 1688 1688 2160
PLL long-term time jitter is measured at the end of the video line, where it is at its maximum.
tCPH n CKDATA
tCPL 50% tsu(d)(o) 2.4 V
DATA
In-1
In
In+1
0.4 V th(o) td(s) Sample n+1 Sample n Sample n+2 Sample n+3
FCE700
Vin
Fig 10. Data timing; Dmx = 0; n = even pixel.
RGBIN
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
CKADC
CKDATA
OUT A
n-2
n-1
n
n+1
n+2
n+3
n+4
n+5
FCE701
Fig 11. Timing diagram; single port mode; Dmx = 0, Ckdd = 0, Ckdp = 0; n = even pixel.
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Triple 8-bit ADC 170 Msps
RGBIN
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
CKADC
CKDATA
OUT A
n-2
n
n+2
n+4
OUT B
n-1
n+1
n+3
FCE702
Fig 12. Timing diagram; dual port mode, interleaved outputs, even pixels on port A; Dmx = 1, Shift = 1, Odda = 0, Ckdd = 0, Ckdp = 0; n = even pixel.
RGBIN
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
CKADC
CKDATA
OUT A
n-1
n+1
n+3
OUT B
n-2
n
n+2
n+4
FCE703
Fig 13. Timing diagram; dual port mode, interleaved outputs, odd pixels on port A; Dmx = 1, Shift = 1, Odda = 1, Ckdd = 0, Ckdp = 0; n = even pixel.
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Preliminary data
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Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
RGBIN
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
CKADC
CKDATA
OUT A
n-4
n-2
n
n+2
OUT B
n-3
n-1
n+1
n+3
FCE704
Fig 14. Timing diagram; dual port mode, synchronized outputs, even pixels on port A; Dmx = 1, Shift = 0, Odda = 0, Ckdd = 0, Ckdp = 0; n = even pixel.
RGBIN
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
CKADC
CKDATA
OUT A
n-1
n+1
n+3
n+5
OUT B
n-2
n
n+2
n+4
FCE705
Fig 15. Timing diagram; dual port mode, synchronized outputs, odd pixels on port A; Dmx = 1, Shift = 0, Odda = 1, Ckdd = 0, Ckdp = 0; n = even pixel.
9397 750 09457
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Preliminary data
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Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
13. Application information
68 nF
150 pF
n.c. VCCA(PLL) AGNDPLL
VCCO(PLL)
AGNDPLL
OGNDPLL A7R
CKREFO
ORR VCCO(R) OGND R 111 VCCO(R)
113 112
CKDATA
144
143
142
141
140
139
138
137
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
110
136
109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72
OGNDR n.c. B7R B6R B5R B4R B3R B2R B1R B0R A7G A6G A5G A4G A3G A2G A1G A0G ORG VCCO(G) OGNDG VCCO(G) OGNDG B7G B6G B5G B4G B3G B2G B1G B0G A7B A6B A5B A4B A3B A2B
GNDDP
HSYNC
DGND1 n.c.
COAST
CKREF
TESTO
CKEXT
n.c. VCCD1
A6R
A5R
A4R
A3R
A2R
A1R
n.c.
10 nF 10 nF
2 VREF 3 DEC1 4 AGCR 5 10 nF BOT R 6 22 nF GAINCR 7 4.7 nF CLP R 8 10 nF DECR 9 VCCA(R) 10 100 nF INR RIN 11 n.c. 12 AGNDR 75 or 50 13 n.c. 14 AGCG 15 10 nF BOTG 16 22 nF GAINCG 17 4.7 nF CLP G 18 10 nF DECG 19 VCCA(G) 20 100 nF ING GIN 21 AGNDG 22 INSOG 75 or 50 GIN 23 SOGO 470 nF 24 n.c. 25 AGCB 26 10 nF BOT B 27 22 nF GAINCB 28 4.7 nF CLP B 29 10 nF DECB 30 VCCA(B) 31 100 nF INB BIN 32 AGNDB 33 n.c. 75 or 50 34 n.c. 35 n.c. 36
DEC2
1
TDA8757HL
I2C/3W 37 A1
38
39
40
41
42
43
VDDD 45 VSSD1
44
46
47
48
n.c. 49 n.c. 50 n.c.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
OGND B 66 VCCO(B)
65
67
A0R
CLP
INV
OE
PD
CP
CZ
68
69
70
n.c.
VCCO(B)
OGND B
VCCD2
n.c.
n.c.
ORB
B0B
B1B
B2B
B3B
B4B
B5B
B6B
B7B
A0B
TCK
TDO
SEN
SDA
DGND2
VSSD2
VSSD3
A1B
A2
DIS
SCL
71
(tbf)
10 k
VPU
10 k
VPU
005aaa010
For interfacing the 5 V digital outputs of TDA8757 to devices with 3 V compliant inputs, a resistor bridge (220 in series, 820 to ground) should be applied to each digital output.
Fig 16. Application diagram.
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(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Preliminary data
Rev. 07 -- 28 February 2002
31 of 37
Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
14. Package outline
HLQFP144: plastic thermal enhanced low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm; exposed die pad SOT612-1
c
y X
Dh 108 109 73 72 ZE
A
e
Eh
E HE
A A2
A1
(A 3) Lp L detail X
wM bp pin 1 index 144 1 wM D HD ZD B vM B 36 bp vM A 37
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 20.1 19.9 Dh 7.1 6.9 E(1) 20.1 19.9 Eh 7.1 6.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 ZD(1) ZE(1) 1.4 1.1 1.4 1.1 7o 0o
22.15 22.15 21.85 21.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT612-1 REFERENCES IEC JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-03-22 02-01-25
Fig 17. Package outline.
9397 750 09457 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Preliminary data
Rev. 07 -- 28 February 2002
32 of 37
Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
15. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it is desirable to take normal precautions appropriate to handling integrated circuits.
16. Soldering
16.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
16.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C small/thin packages.
16.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board.
9397 750 09457 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Preliminary data
Rev. 07 -- 28 February 2002
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Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle
to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
16.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
16.5 Package related soldering information
Table 19: Suitability of surface mount IC packages for wave and reflow soldering methods Package BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC[3], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO
[1]
Soldering method Wave not suitable not suitable[2] Reflow[1] suitable suitable suitable suitable suitable
suitable not recommended[3][4] not recommended[5]
[2]
[3] [4] [5]
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Preliminary data
Rev. 07 -- 28 February 2002
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Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
17. Revision history
Table 20: Revision history Rev Date 07 20020228 CPCN Description Preliminary data (9397 750 09457); seventh version
9397 750 09457
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Preliminary data
Rev. 07 -- 28 February 2002
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Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
18. Data sheet status
Data sheet status[1] Objective data Preliminary data Product status[2] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] [2]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
19. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
21. Licenses
Purchase of Philips I2C components
20. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
Contact information
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
9397 750 09457
Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Preliminary data
Rev. 07 -- 28 February 2002
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Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 9 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.1.8 9.1.9 9.2 9.3 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 16.5 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . 11 Analog video inputs . . . . . . . . . . . . . . . . . . . . 11 Clamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Variable gain amplifiers . . . . . . . . . . . . . . . . . 13 Important recommendations . . . . . . . . . . . . . . 13 ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C-bus and 3W-bus interfaces . . . . . . . . . . . . 17 Register definitions . . . . . . . . . . . . . . . . . . . . . 17 Subaddress. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Offset register . . . . . . . . . . . . . . . . . . . . . . . . . 17 Coarse and Fine registers . . . . . . . . . . . . . . . 18 Control register . . . . . . . . . . . . . . . . . . . . . . . . 19 VCO register . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Divider register . . . . . . . . . . . . . . . . . . . . . . . . 20 Phase register. . . . . . . . . . . . . . . . . . . . . . . . . 20 DEMUX register . . . . . . . . . . . . . . . . . . . . . . . 21 Power-down mode . . . . . . . . . . . . . . . . . . . . . 21 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21 3W-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 22 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 22 Thermal characteristics. . . . . . . . . . . . . . . . . . 23 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 23 Application information. . . . . . . . . . . . . . . . . . 31 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 32 Handling information. . . . . . . . . . . . . . . . . . . . 33 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 33 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 33 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 34 Package related soldering information . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 35 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 36 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 20 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
(c) Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 28 February 2002 Document order number: 9397 750 09457

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